1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a field emission device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for forming a field emission device having a multistage electrode.
2. Discussion of the Related Art
A field emission is defined as electrons emitted by an electric field. The emission of electrons is caused by a quantum-mechanical tunnelling effect. The tunnelling occurs when a potential barrier becomes shallow while applying a high potential energy on the surface of a metal. Thus, electrons positioned at the Fermi level can directly pass through the potential barrier without overcoming the potential barrier.
FIGS. 1 and 2 schematically illustrate a conventional single electrode field emission device and a conventional micro-column electron beam lithography system, respectively.
There are two kinds of electron sources using the field emission: a single electrode field emission device comprising a tip 1 and a single gate electrode 2, as shown in FIG. 1; and a multistage electrode field emission device comprising a tip and a multistage electrode for effective focusing or acceleration of the emitted electrons.
In the single electrode field emission device, various fabricating methods for realizing both repeatability and reliability have been developed. Nonetheless, these devices have limitations in focusing and acceleration of the field emission.
Moreover, it is difficult to integrate at least two electrodes on one wafer in the multistage electrode field emission device. Accordingly, a conventional method of embodying the multistage electrode field emission device is to fabricate each of the chip and the multistage electrode separately and then assemble the two together. For example, as shown in FIG. 2, a previously manufactured field emission tip 4, which is manually aligned and assembled with multistage electrode 5, and lens group 6, for focusing the emitted field, are manually assembled to complete the device.
Therefore, in the conventional micro-column electron beam lithography system, because alignment and assemblies between tip and gate electrode or between electrodes are achieved by manual operation, the system is not capable of providing better characteristics in repeatability, uniformity and productivity. In addition, the system cannot achieve a complete symmetrical structure. As a result, a desirable optical characteristic is not produced properly. Although the micro-column array concept has been introduced to improve a major problem in the electron beam lithography system such as low productivity, uniformity and repeatability of the system have not improved and should not be ignored.
Therefore, research for performing an automatic alignment of the multistage electrode and the field emission tip and for integrating them on one wafer have been developed in order to solve the above-mentioned problems. One line of research has been focused on utilizing a straight line of flight deposition characteristic to align the multistage electrode automatically.
A conventional multistage electrode field emission device will now be described with reference to FIGS. 3A to 3F.
FIGS. 3A to 3F are cross-sectional views sequentially illustrating the process steps of fabricating a conventional multistage electrode field emission device.
As shown in FIG. 3A, a first silicon oxide layer (SiO.sub.2) 12 and a first photoconductive layer 13 are sequentially deposited on a silicon substrate 11. After a tip portion is defined by exposure and developing process, the first silicon oxide layer 12 is selectively removed.
In FIG. 3B, the silicon substrate 11 is anisotropically-etched to have a predetermined depth by using a patterned first silicon oxide layer 12 as a mask. A thermal oxide layer 14 is formed by thermally oxidizing a surface of the etched silicon substrate 11. In this process, a portion of the silicon substrate 11 below the first silicon oxide layer 12 forms the thermal oxide layer 14 having a sharp point.
FIG. 3C shows a second silicon oxide layer (SiOx) 15 and a first metallic layer 16, for example, niobium (Nb), which are sequentially deposited on the first silicon substrate 12 and the silicon substrate 11. In this process, since the second silicon oxide layer 15 and the first metallic layer 16 are deposited by an evaporator having the straight line of flight deposition characteristic, the layers 15 and 16 are discontinuously deposited on both the first silicon oxide layer 12 and the silicon substrate 11 positioned at both sides of the first silicon oxide layer 12.
As shown in FIG. 3D, a second photoconductive layer 17 for defining a pad region is formed on the first metallic layer 16 positioned at one side of the first silicon oxide layer 12.
A third silicon oxide layer 18 and a second metallic layer 19, for example, niobium (Nb), are sequentially deposited on the second photoconductive layer 17 and the first metallic layer 16 as shown in FIG. 3E. In this process, the third silicon oxide layer 18 and the second metallic layer 19 are discontinuously deposited on the second photoconductive layer 17, the first metallic layer 16 on the first silicon oxide layer 12, and the first metallic layer 16 on the silicon substrate 11.
As shown in FIG. 3F, the second photoconductive layer 17 and the third silicon oxide layer 18 and the second metallic layer 19 on the second photoconductive layer 17 are removed. Also, the first silicon oxide layer 12 and the second silicon oxide layer 15, the first metallic layer 16, the third silicon oxide layer 18 and the second metallic layer 19 on the first silicon oxide layer 12 are selectively removed.
Then, an exposed portion of the thermal oxide layer 14 is selectively removed so that a sharp point of the silicon substrate 11 is exposed for fabricating the field emission device. The sharp point becomes an emitter of the field emission device.
However, this conventional art for fabricating the field emission device has the following problems.
In the conventional art, a silicon oxide layer and a metallic layer are formed by using a device having the straight line of flight deposition characteristic, so that the deposition of the layers is not uniform on all areas of the substrate. In other words, since the conventional art utilizes a point deposition source having the straight line of flight deposition characteristic, angles from the source to the wafer vary with distance from the center of the wafer. As a result, deposited layers tend to be a non-uniform structure.
Moreover, the silicon oxide layer fabricated by the conventional art is coarse and has poor crystallographic quality. In addition, since the silicon oxide layer has a high etching rate in an etching solution, such as a HF solution, the fabricating process becomes difficult and complicated.
Further, since a dielectric breakdown easily occurs, even in a low voltage in the conventional art, the range of voltages to be applied is a narrow limit.